1. Technical Field
Various embodiments generally relate to a sense amplifier driving device, and more particularly, to a technology for improving the post overdriving operation characteristic of a semiconductor device.
2. Related Art
Semiconductor memory devices are being developed to increase the degree of integration and the operating speeds of the semiconductor memory devices. In order to increase the operating speeds of the semiconductor memory devices, a synchronous memory device has been developed. This synchronous memory device is capable of operating in synchronization with a clock signal received from outside a memory chip.
For example, an SDR (single data rate) synchronous memory device may be implemented whereby data is inputted and outputted through a single data pin during a single clock cycle. In the SDR synchronous memory device, the input and output of the data is in synchronization with the rising edge of a clock signal.
However, the SDR synchronous memory device has difficulty in operating with systems which require high speed operations. Accordingly, a DDR (double data rate) synchronous memory device may be implemented whereby data is consecutively inputted and outputted through each data input/output pin, in synchronization with the rising edge and the falling edge of a clock signal.
As such, a bandwidth at least two times wider than the conventional SDR synchronous memory device may be realized without increasing the frequency of a clock signal, and thus, a high speed operation may be achieved.
Among semiconductor memory devices, a DRAM (dynamic random access memory) is a representative volatile memory. The memory cell of the DRAM is constructed by a cell transistor and a cell capacitor.
The cell transistor functions to control an access to the cell capacitor, and the cell capacitor stores charges corresponding to data. That is to say, according to the amount of the charges stored in the cell capacitor, data of a high level or data of a low level is determined.
If a word line is activated in a semiconductor memory device, charge sharing occurs between a bit line and a bit bar line, and then, a sense amplifier operates. The sense amplifier performs initially an overdriving operation by using an external voltage VDD for a predetermined pulse period, such that the bit line or the bit bar line may quickly reach a target voltage level.
In this regard, as the power supply voltage of a semiconductor memory device gradually decreases, a core voltage (VCORE) decreases as well. Due to this fact, as the amount of charges of the cell of a DRAM decreases, the refresh and tWR (a time during which a precharge command may be applied after a point of time at which a write command is applied) characteristics of the DRAM may deteriorate.
In order to cope with this problem, a post overdriving (POD) operation is performed, in which the charging voltage of the cell is momentarily increased during only the final part of a period in which charges are transferred to the cell. However, an external voltage may be a high voltage or a low voltage according to a system. Therefore, in the case where the POD operation is performed regardless of the level of a power supply voltage, an efficient sense operation may not be performed.
In other words, if a power supply voltage is high, as a pair of bit lines are excessively overshot, unnecessary current consumption is caused. Conversely, if the power supply voltage is low, the bit line or the bit bar line may not quickly reach the target voltage level, and thus, the stable speed of the semiconductor memory device may not be ensured.